Image Rate Based Cross Layer Optimizations for Image Delivery in Wireless Sensor Networks (285-297)  
        H.-G. Wang, D.-M. Peng, W. Wang, and H. Sharif 
A number of growing sensor applications such as target tracking and health monitoring motivate rate-based image transmissions in the Wireless Sensor Network (WSN). In this paper, we propose a cross layer based optimal approach for image sensors to decide transmission patterns based on a Rate-Oriented Routing scheme, which achieves both high energy efficiencies and longer network lifetime. In this approach, a group of image sensors transmit the images through appropriate rate-based routing paths under the user requirements. The simulation results show that the proposed image transmission scheme can achieve considerable gains in terms of the WSN energy efficiency and network lifetime extension.

TSFD: Two Stage Frame Dropping for Scalable Video Transmission over Data Networks  (298-313)  
        B. Zheng and M.  Atiquzzaman  
Scalable video transmission is requried to transmit video over bandwidth limited channel like the Internet. However, previous scalable video transmission schemes which are based on static priority layer/slice encapsulation did not provide an algorithm to optimally choose parameters and/or required changes in the standard network protocol. The objective of this paper is to develop a new scalable video transmission scheme which can transmit stored video with low bandwidth requirement and eliminate the underflow/overflow at client to ensure QoS. The main contributions in our scheme are: parameters are chosen based on the bit rate and burstiness of video, video frames are priority encapsulated and dropped dynamically by the server and/or network depending on the network congestion, the need for decoder/encoder combination at the server is eliminated, and no major changes are required in the standard network protocol. An analytical model is developed to determine the performance and quality of service offered by our proposed scheme as the function of the network size, network congestion level, and video burstiness. Results show that our scheme requires low bandwidth as a function of network size, network congestion level and video burstiness.

Performance of a H.264/AVC Error Detection Algorithm Based on Syntax Analysis  (314-330)  
        L. Superiori, O. Nemethova, and M. Rupp  
In this work we investigate the possibility of detecting errors in H.264/AVC encoded video streams. We propose a method for the detection of errors exploiting the set of entropy coded words as well as range and significance of the H.264/AVC information elements. We evaluate the performance of such syntax analysis based error detection technique for different bit error probabilities and compare it to the typical packet discard approach. Particular focus is given on low rate video sequences.

An Intelligent Call Admission Control System for Wireless Cellular Networks Based on Fuzzy Logic  (331-346)  
        L. Barolli  
The mobile cellular systems are expected to support multiple services with guaranteed Quality of Service (QoS). However, the ability of wireless systems to accommodate expected growth of traffic load and broadband services is limited by available radio frequency spectrum. Call Admission Control (CAC) is one of the resource management functions, which regulates network access to ensure QoS provisioning. However, the decision for CAC is very challenging issue due to user mobility, limited radio spectrum, and multimedia traffic characteristics. To deal with these problems, in this paper, we propose a fuzzy CAC system. We compare the performance of the proposed system with Shadow Cluster Concept (SCC). We evaluate by simulation the performance of the proposed system. The proposed system has a good behavior on deciding the number of accepted connections while keeping the QoS for serving connections.

Dual-Execution Mode Processor Architecture For Embedded Applications (347-370)  
        Md. M. Akanda, B.A. Abderazek, and M. Sowa  
This paper presents a novel embedded 32-bit processor architecture targeted for mobile and embedded applications. The processor supports Queue and Stack based programming models in a single simple core. The design focuses on the ability to efficiently execute Queue programs and also to support Stack programs without a considerable increase in hardware to the base Queue architecture.
A prototype implementation of the processor is produced by synthesizing the high level model for a target FPGA device. We present the architecture description and design results in a fair amount of details. From the design and evaluation results, the QSP32 core efficiently executes both Queue and Stack based programs and achieves on average about 65MHz speed. In addition, when compared to the base single-mode architecture (PQP), the QSP32 core requires only about 2.54\% additional hardware.                      

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